The present invention relates to a sense amplifier, and, more specifically, to a single-ended sense amplifier with improved biasing and clocking.
Programmable Logic Arrays (PLA) are an efficient manner of implementing random logic functionality in a non-custom integrated circuit. A typical PLA contains gates arrayed in a programmable matrix with many data input terminals and data output terminals presented for use when using the PLA in a system. The output of each logic path within the array is prepared for external use by a sense amplifier. The sense amplifier detects the data output state of each logic path within PLA array and buffers it for use by circuitry external to the PLA proper.
Prior applications of PLAs have traditionally used differential logic paths. Each logic path is physically represented by a data signal, D, and a logical compliment of the data signal, D#. The use of the differential logic paths provided superior common-mode noise rejection. As part of using differential logic paths, differential sense amplifiers were used in these PLAs. These differential sense amplifiers provided a differential input with terminals for D and D# signals, and provided complimentary output terminals for output data signals O and output data compliment signals O#.
Newer requirements for PLA design include much higher speed and the use of low voltage swing (LVS) logic levels. These requirements have made the necessity of providing sufficient circuitry to implement both a D and a D# signal path in each logic path of the PLA burdensome, both in terms of propagation delay tolerances and in terms of area required on the chip. It would be possible to use a single-ended sense amplifier, one with only a D input terminal, to eliminate the necessity of providing both a D and a D# signal path in each logic path. However, shortcomings have been shown in the use of traditional single-ended sense amplifier designs in an LVS design. The difference between the two signaling voltages in an LVS design, xcex94V, is not tightly controlled in an LVS design. The xcex94V may vary from one wafer to another with differences in process. Moreover, the value of xcex94V may be only hundreds of millivolts, not the volts of other logic families.